library ieee;
use ieee.std_logic_1164.all;

-- do not change this entity
-- yes the signal lengths are correct
entity mycpu is
  port (
    -- clock signal
    CLK      : in  std_logic;
    -- reset for processor
    nReset   : in  std_logic;
    -- halt for processor
    halt     : out std_logic;
    ramAddr  : out std_logic_vector(15 downto 0);
    ramData  : out std_logic_vector(31 downto 0);
    ramWen   : out std_logic;
    ramRen   : out std_logic;
    ramQ     : in  std_logic_vector(31 downto 0);
    ramState : in  std_logic_vector(1 downto 0)
    );
end mycpu;

architecture behavioral of mycpu is

  -- you may change the entity of your component
  -- as well as the signal names
  component cpuStruct
   port (
    -- clock signal
    CLK      : in  std_logic;
    -- reset for processor
    nReset   : in  std_logic;
    -- halt for processor
    halt     : out std_logic;
    ramAddr  : out std_logic_vector(15 downto 0);
    ramData  : out std_logic_vector(31 downto 0);
    ramWen   : out std_logic;
    ramRen   : out std_logic;
    ramQ     : in  std_logic_vector(31 downto 0);
    ramState : in  std_logic_vector(1 downto 0)
    );

  end component;

  signal nclk : std_logic;
begin

    nclk <= not CLK;

  theCPU : cpuStruct
    port map (nCLK, nReset, halt, ramAddr,ramData,ramWen,ramRen,ramQ,ramState);

end behavioral;
